tinyCLUNX33
System on Module with CrosslinkU-NX
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Source | Release | Zephyr Example
The RTL Reference Design is a set of Verilog sources (sometimes generated from another HDL) providing common design elements for building an application on top of the SoM hardware.
Once completed, it will usable as a stand-alone design for implementing a product, or as a base to build upon.
To build this component, refer to the RTL build instructions.
For RTL engineers, the Reference Design is presented as a single module providing a data communication interface for the feed that goes through USB.
TODO: present example Verilog instantiation illustrating this
The RTL reference design is made out of two independent parts (Data Pipeline, CPU SoC), and an interface for inserting custom data processing at ease:
The user does not need to customize this part, although it is possible.
External ports:
Internal AXI64 cores:
The user does not need to customize this part, although it is possible.
External ports:
Internal Wishbone cores:
The interface for moving large amounts of data from custom RTL to the USB core is a standard AXI64 slave. Specific configuration and addresses for AXI access are controlled by the corresponding USB endpoint configuration in the Zephyr driver.
Helper cores available MIPI/USB/RAM:
If the FPGA bitfile gets loaded successfully and is being enabled in the FPGA, then the DONE LED will be lit-up.
If it is not lit, you probably did not program the FPGA properly. Please program the FPGA using the instructions provided.
Make sure to also load a Zephyr Example Release matchiing the RTL Reference Design version you programmed.
Check also the flash offset at which you program things.
Make sure to power cycle the board right after programming it.
The RTL Reference Design uses a flash in qSPI mode. For this to work, a special Quad Enable (QE) bit needs to be set in the flash via SPI commands, i.e. done by the FTDI.
Once this is active, this stays in the flash until it is changed. This is usually done by tinytVision.ai at the factory.
If you are an early user, you might require to do this yourself.
This can be done, for instance, with the Radiant Programmer software part of the Radiant package, instead of using ecpprog
.
The flash documentation explains how to use the Radiant Programmer to do it.
There are many possibilites! Here are a few:
You can use Linux, Radiant has a Linux installation available.
Lattice Radiant does not currently support Mac OS. It is possible to use a Windows or Linux virtual machine and run Radiant inside.
RISCV firmware and FPGA bitfiles can be programmed using either Radiant or ecpprog
which is included with the OSS CAD Suite toolchain.
For any changes to the FPGA or to recompile the FPGA or to use it for debug, you will need the Radiant tool license which is free and available from the Lattice website.
Note that you may require additional licenses to complete your work. For example, MIPI related components, which you can request from Lattice.
For more details on how to flash the firmware, please refer to SoM Flash.